The present invention generally relates to a turbo decoder. More specifically, the present invention relates to a method and apparatus for buffering an encoded signal for a turbo decoder in a communication network.
Advance communication systems, which are prone to interference and channel variations, employ forward error correcting (FEC) codes to minimize bit errors and/or improve energy efficiency. In a typical FEC encoder/decoder system, data is encoded by adding some redundant bits to the data. The redundant bits are then transmitted along with the data over a physical channel. At the receiving end, a FEC decoder tries to correct the bit errors, if any, in the received data by exploiting the redundant bits. If more redundant bits are added to the data, the code becomes more powerful. However, the data communication becomes less efficient due to reduction in the ratio of information bits to the total bits transmitted over the physical channel. Additionally, more number of processing cycles is required on both transmitting and receiving ends of the communication system when more redundant bits are added for encoding the data. Turbo code is one of the most powerful FEC codes known today due to its high coding efficiency at relatively manageable complexity.
In a typical turbo encoder, an encoding module receives specified number of information bits and generates a codeword. The codeword comprises original information bits, called systematic bits, and redundant bits, called parity bits. The codeword is typically organized as one or more data sub-blocks comprising only the systematic bits followed by one or more parity sub-blocks comprising only the parity bits. Initially, each sub-block in the codeword is of same size.
An example of the encoding module can include, but not limited to, a binary or duo-binary circular recursive systematic convolutional encoding module. FIG. 1 is a block diagram of a duo-binary encoding module of a typical turbo codec system. Duo-binary encoding module 100 includes an interleaver 102, an encoding unit 104 and an encoding unit 106. Encoding unit 104 receives a data sub-block A and data sub-block B and generates parity sub-block Y1 and parity sub-block W1. Interleaver 102 changes the sequence of information bits in data sub-block A and data sub-block B and outputs the corresponding interleaved data sub-blocks to encoding unit 106. Encoding unit 106 generates an interleaved parity sub-block Y2 and an interleaved parity sub-block W2. A serializing unit 108 receives all the data sub-blocks and parity sub-blocks and outputs a codeword. Each of these sub-blocks comprises N bits. For 2N information bits, duo-binary encoding module 100 generates 6N bits, therefore its native code rate is ⅓.
FIG. 2 is a block diagram of a typical turbo codec system 200. Turbo codec system 200 includes a turbo encoder 202 and a turbo decoder 204. An encoding module 206 receives information bits and outputs a codeword. The codeword includes one or more data sub-blocks comprising information bits and one or more parity sub-blocks comprising parity bits. A sub-block interleaving module 208 changes the bit sequence of each sub-block of the codeword using an identical permutation formula. Sub-block interleaving module 208 is a second level interleaver in addition to the interleaver provided within encoding module 206. Having multiple levels of interleaving increases the complexity of the code and hence the coding efficiency. However, it increases the storage requirements at the receiving end of the communication system as the decoder cannot start processing the codeword until is completely de-interleaved.
After sub-block interleaving, depending upon the varying channel conditions, a puncturing module 210 punctures the codeword to improve its code rate from the native code rate of encoding module 206. Puncturing is achieved by removing one or more parity bits of one or more parity sub-blocks in the codeword. For example, if channel conditions are favorable, code rate can be increased by removing more parity bits as less number of bit errors are expected to occur and hence even with smaller set of parity bits, decoder can correct the bit errors. On the contrary, if channel conditions are bad, decoder may not be able to correct all the bit errors even with complete set of parity bits and hence either less number of parity bits or no parity bits should be discarded. For example, for fixed wireless applications with good channel conditions, the code rate can be made as high as ⅚.
Thereafter, the codeword is transmitted to turbo decoder 204 of a receiver through a physical channel 212. Turbo decoder 204 includes a sub-block de-interleaving module 216, an input buffer 218, a read logic 220 and a decoding module 222. At turbo decoder 204, the information bits and the parity bits are represented as Log-Likelihood Ratios (LLRs). LLR is a soft estimate of the symbol received at turbo decoder 204. The soft estimate indicates the probability of the received symbol being close to 1 or 0. Therefore, the codeword received at turbo decoder 204 is a sequence of data LLRs and parity LLRs and not the sequence of information bits and parity bits. The reason for representing the information bits and parity bits as LLRs is that a Soft-In-Soft-Out (SISO) processor of decoding module 222 is designed to work on soft-data only. The width of the LLR can vary depending upon the channel conditions. However, for most of the applications 8-bit width is more than sufficient for representing the LLR.
In order to be decoded by decoding module 222, the sequence and number of LLRs of the received codeword must be identical to those of the codeword generated by turbo encoder 202. Therefore the effects of puncturing and sub-block interleaving have to be annulled before passing the received codeword to the decoding module 222. De-puncturing module 214 inserts a pre-defined value in place of the parity bits removed from the codeword during puncturing to restore the native code rate of encoding module 206. For example, the native code rate of encoding module 206 is ⅓ and the code rate of the codeword after puncturing is ½. This implies that two parity sub-blocks of the codeword were completely removed during puncturing. In this case, to restore the native code rate, i.e., ⅓, de-puncturing module 214 inserts a predefined value in place of each parity bit which was removed by completely puncturing the two parity sub-blocks.
The SISO processor of decoding module 222 cannot start processing until the de-punctured codeword is sub-block de-interleaved and stored in input buffer 218. Therefore, a sub-block de-interleaving module 216 de-interleaves each sub-block of the codeword to re-establish the original sequence of bits within each sub-block. Thereafter, each sub-block of the codeword received at turbo decoder 204 is stored in input buffer 218. A considerable number of cycles are spent in storing the codeword if the codeword size is large. In IEEE802.16e, the maximum permissible size of the codeword is 14400 bits. This adds to the input latency of decoding process and adversely affects the overall processing time of turbo decoder 204. Several implementation strategies have been proposed to bring down the processing cycles of SISO processor but very little or no effort has been invested to bring down the input latency.
Accordingly, what is a needed is an improved turbo decoder which has low input latency for code rates which are higher than the native code rate of the encoding module.